Generally, semiconductor memory devices often have low drivability due to conditions related to process changes. In such a case, drivability of a voltage is also decreased, causing a large change in internal voltages. The change in the internal voltages results in erroneous operation of semiconductor memory devices.
As semiconductor memory devices are being highly integrated, process conditions are also changing to a great extent. Thus, a core voltage decreases, and this decreasing core voltage leads to decrease in drivability of a bit line precharge voltage and a cell plate voltage.
FIG. 1 is a circuit diagram of a conventional voltage generator designed to generate a bit line precharge voltage.
The conventional voltage generator includes a core voltage controller 10 and a voltage driver 20. The core voltage controller 10 includes a core voltage generation block 11, a bias voltage generation block 12 and a gate voltage generation block 13.
The core voltage generation block 11 generates one half of a core voltage VCORE that becomes a reference voltage of a bit line precharge voltage VBLP or a cell plate voltage (not shown). The core voltage generation block 11 includes P-type channel metal-oxide semiconductor (PMOS) transistors P1 and P2 and resistors R1 and R2. The PMOS transistors P1 and P2 and the resistors R1 and R2 are connected in series between a terminal of the core voltage VCORE and a terminal of a ground voltage VSS. A reference voltage VREF is generated by a voltage divider using resistance from a self-bias diode and resistance from lines.
When a power supply voltage is supplied from an external source, the voltage divider illustrated in FIG. 1 is used to generate a power voltage. However, when the power supply voltage is generated within an internal device, the reference voltage VREF can be generated through a reference voltage generator from another apparatus.
The bias voltage generation block 12 generates bias voltages PBIAS and NBIAS using the reference voltage VREF. The bias voltage generation block 12 includes PMOS transistors P3 to P6 and N-type channel metal-oxide semiconductor (NMOS) transistors N1 to N6. The PMOS transistor P3 and the NMOS transistors N1 and N3 are connected in series between the terminal of the core voltage VCORE and the terminal of the ground voltage VSS, and thus, current consistently flows to the terminal of the ground voltage VSS. The reference voltage VREF is supplied to a gate of the PMOS transistor P3, and a gate and one terminal of the NMOS transistor N1 are connected with each other, and the same connection is applied to the NMOS transistor N3.
The PMOS transistor P4 and the NMOS transistors N2 and N4 are connected in series between the terminal of the core voltage VCORE and the terminal of the ground voltage VSS, thereby being configured as in a current mirror circuit. Due to this configuration, current flows consistently to the terminal of the core voltage VCORE. A gate and one terminal of the PMOS transistor P4 are connected with each other, and gates of the NMOS transistors N1 and N2 are connected with each other. A gate of the NMOS transistor N3 is connected with a gate of the NMOS transistor N4. Due to this connection architecture, the same current flows to the NMOS transistors N2 and N4.
The PMOS transistor P5 is connected between the terminal of the core voltage VCORE and an NMOS transistor N7. Gates of the PMOS transistors P4 and P5 are connected together, forming a current mirror circuit. The PMOS transistor P6 is connected between the terminal of the core voltage VCORE and an NMOS transistor N8, and the bias voltage PBIAS is supplied to a gate of the PMOS transistor P6. The NMOS transistor N5 is connected between the terminal of the ground voltage and the PMOS transistor P7, and the bias voltage NBIAS is supplied to a gate of the NMOS transistor N5. The NMOS transistor N6 is connected between the terminal of the ground voltage and the PMOS transistor P8, and the bias voltage NBIAS is supplied to a gate of the NMOS transistor N6.
The gate voltage generation block 13 includes the NMOS transistors N7 and N8 and PMOS transistors P7 and P8. A gate voltage NGATE is supplied to gates of the NMOS transistors N7 and N8 that are connected with each other. A gate voltage PGATE is supplied to gates of the PMOS transistors P7 and P8 that are connected commonly with each other. That is, the NMOS transistors N7 and N8 and the PMOS transistors P7 and P8 are configured as a current mirror circuit. The gate voltage generation block 13 generates the gate voltages NGATE and PGATE. The gate voltage NGATE has a voltage level greater than the reference voltage VREF by a voltage level of a threshold voltage of the NMOS transistor N7. The gate voltage PGATE has a voltage level less than the reference voltage REF by a voltage level of a threshold voltage of the PMOS transistor P7.
The voltage driver 20 includes a PMOS transistor P9 and an NMOS transistor N9. The PMOS transistor P9 and the NMOS transistor N9 are connected in series between the terminal of the core voltage VCORE and the terminal of the ground voltage VSS. A Pull-up signal PDRV and a pull-down signal NDRV are supplied to respective gates of the PMOS transistor P9 and the NMOS transistor N9. A bit line precharge voltage VBLP is output through a common terminal between the PMOS transistor P9 and the NMOS transistor N9.
FIG. 2 is a voltage waveform diagram of the conventional voltage generator illustrated in FIG. 1.
The PMOS transistor P6 operates due to a turn-on resistance whose value is close to a threshold voltage, thereby allowing current to flow consistently. Therefore, since the PMOS transistor P6 operates usually all the time, the turn-on resistance is set high. As a voltage level of the bit line precharge voltage VBLP changes, the NMOS transistor N8 operates like a source follower. Thus, the NMOS transistor N8 operates rapidly.
If a voltage level of the bit line precharge voltage VBLP decreases, voltage levels of the gate voltage NGATE of the NMOS transistor N8 and the bit line precharge voltage VBLP increase. Thus, current flows rapidly to the NMOS transistor N8, and this rapid current flow causes the voltage level of the pull-up signal PDRV to decrease. As a result, the PMOS transistor P9 turns on, resulting in increase in the voltage level of the bit line precharge voltage VBLP.
The NMOS transistor N6 operates due to a turn-on resistance whose value is close to the threshold voltage. Therefore, since the NMOS transistor N6 operates usually all the time, the turn-on resistance is set high. As a voltage level of the bit line precharge voltage VBLP changes, the PMOS transistor P8 operates like a source follower. Thus, the PMOS transistor P8 operates rapidly.
If a voltage level of the bit line precharge voltage VBLP increases, voltage levels of the gate voltage PGATE of the PMOS transistor P8 and the bit line precharge voltage VBLP increase. Thus, current flows rapidly to the PMOS transistor P8, and this rapid current flow causes the voltage level of the pull-down signal NDRV to increase. As a result, the NMOS transistor N9 turns on, resulting in decrease in the voltage level of the bit line precharge voltage VBLP.
The conventional voltage generator is used to improve the drivability. The PMOS transistor P9 and the NMOS transistor N9, having a very low threshold voltage, are included in the voltage driver 20 to increase the drivability of the last terminal. This configuration improves reading and writing operations in an active state; however, when in a precharge state, current is more likely to leak.
In detail, if a threshold voltage level of the PMOS transistor P9 is less than a target voltage level, a standby current is generated due to a large amount of the off-state leakage current. The standby current may result in negative effects. For instance, the standby current may be an issue in low power or mobile products.
Therefore, if threshold voltages of the PMOS transistor P9 and the NMOS transistor N9 are lowered to secure an operation region of the last driver terminal, the drivability can be improved, but severe damage may arise in respect of the standby current.
Also, if the bit line precharge voltage VBLP is not stable or the voltage generator operates during a standby mode, the PMOS transistor P8 operates like a source follower. Thus, the voltage driver 20 turns on fast, and turns off slowly since a minimum amount of current is supplied to reduce the standby current.
Accordingly, two points of turning on and turning off the last driver terminal are often mismatched. As a result, there may be a case that the PMOS transistor P8 and the NMOS transistor N9 turn on simultaneously, resulting in generation of a direct current.
During the operation, the standby current and the direct current are likely to be generated. Thus, a ringing current may be generated during the standby mode and the operation mode, further decreasing the drivability of semiconductor memory devices.